1. Field of the Invention
The present invention relates to a manufacturing method of semiconductor devices by using a dry etching technology. More particularly, the present invention relates to a method of forming an interlayer insulating film of a dual trench metallization using an organic silicon film such as polysilane, a method of forming a contact hole and a trench, a method forming a deep trench, a method of removing an antireflection film, a method of forming a trench metallization of low interwiring coupling capacitance, and a semiconductor device manufactured by using these methods.
2. Description of the Related Art
When a process for manufacturing semiconductor devices each having a multilayered metallization is performed, a step is frequently employed whereby the pattern of a contact hole or the like is formed on a multilayered insulating film constituted by, for example, a silicon oxide film, silicon nitride film and the like, such that a resist serves as a mask.
Hitherto, when a selective etching step of the silicon oxide film and the silicon nitride film is performed by using dry etching technology such as reactive ion etching (RIE), the selective ratio (the ratio of etching speeds) between the resist and the silicon oxide film can be raised. The selective etching can easily be performed. Since the etching selective ratio between the resist and the silicon nitride film cannot be raised, selective etching of the silicon nitride film using the resist as a mask cannot easily be performed.
In recent years, the integration of miniature trench capacitors at a high density has been required to manufacture large scale semiconductor memory devices. Therefore, formation of trenches each having a great depth compared to the size of the opening portion (hereinafter called a “high aspect ratio”) on a semiconductor substrate by using the anisotropic dry etching is one of the important techniques.
When the trenches each having a high aspect ratio are formed on a semiconductor substrate, also opening portions each having a high aspect ratio must be formed in an insulating film mask by using anisotropic dry etching. Hitherto, a resist mask has been employed to form the opening portions in the insulating film mask. To form opening portions each having a high aspect ratio, gas plasma excited by high power and high frequency radiation must be applied to the resist for a long time.
This leads to a fact that the opening portions in the resist are unevenly deformed. Therefore, a plurality of trenches each having a smooth inner surface and exhibiting satisfactory accuracy cannot easily be formed with a high yield in the semiconductor substrate.
As microfabrication technology progresses, the thickness of the resist must be reduced to raise the resolution of lithography. Since so-called film thinning occurs when the dry etching is performed, the trenches cannot easily be formed.
A common method of manufacturing semiconductor devices incorporates a smoothing process having the steps of forming isolation trenches for isolating devices from one another by using a silicon nitride film, the pattern of which has been formed on a semiconductor substrate as an etching mask, forming a thick silicon oxide film for isolating the devices from each other such that the isolation trenches are buried, and polishing the surface such that the silicon nitride film serves as a stopper (a suppression layer) so that the isolation trenches are buried with the oxide film and the device region is smoothed.
Where a plurality of silicon nitride film stoppers present in portions of high density device regions, the process for smoothing the device region using polishing of the surface enables satisfactory smoothing of the surface such that the isolation trenches are filled with the silicon oxide film. In the portions of low density device regions, the number of silicon nitride film stoppers is insufficiently small. Thus, the silicon oxide film is excessively polished in the smoothing process. As a result, there arises a problem in that smoothing and formation of the device regions cannot be performed uniformly over the overall surface of the wafer.
Therefore, a countermeasure is taken whereby a polysilicon film is deposited on the overall surface, and then a smoothing process is performed and the polysilicon film, as the etching mask, is left in the low density portion. The smoothing step, however, sometimes encounters a crack in the silicon oxide film in the low density portion. When the silicon nitride film stoppers on the device region and the polysilicon mask are removed, there arises a problem in that the silicon substrate is scooped out excessively.
Hitherto, a gate electrode has been formed by a method comprising the steps of forming a silicon nitride film on a metallic film for forming the gate electrode, forming a resist in a gate electrode formation region on the silicon nitride film, using the resist as a mask to form a nitride film, and using the silicon nitride film having a pattern formed after the resist mask has been removed to form the metallic film as the gate electrode.
If the surface of the wafer has an uneven portion, the projecting portions of the surface of the wafer are excessively etched when the pattern of the silicon nitride film is formed. As a result, the metallic film formed below the pattern is undesirably etched, causing a problem to arise in that a gate electrode formation cannot be satisfactorily performed.
When an etching process is performed to form a self-aligned contact (hereinafter abbreviated as a “SAC”), an opening of a contact hole is created in an interlayer insulating film for burying the space between the gate electrode. At this time, an edge line along which the upper surface and the side surface of the gate electrode intersect is exposed in the lower portion of the opening of the contact hole.
Undesirable etching of the gate electrode must be prevented during the etching process for opening the contact hole in the interlayer insulating film constituted by the silicon oxide film. Therefore, the gate electrode is usually coated with a silicon nitride film (an etching stopper) which has a high etching selective ratio with respect to the silicon oxide film. Although a satisfactory high etching selective ratio of the silicon nitride film with respect to the oxide film can be obtained in a flat portion, the etching selective ratio is lowered to about ⅓ or less of the flat portion in the edge line portion.
Therefore, the edge line portion of the gate electrode is undesirably etched when the contact hole is opened in the SAC formation step. Thus, the gate metal is exposed to the outside, causing a short-circuit fault to occur when the metal for the metallization is buried in the contact hole. As a result, it is known that the SAC cannot easily be formed in the process for manufacturing E2 PROM in which the gate electrode has a high aspect ratio (the ratio of the length of the gate and the height of the gate).
Since microfabrication technology has proceeded in recent years, etching of the interlayer insulating film at a high aspect ratio is frequently required. It is known that when dry etching of the silicon oxide film at a high aspect ratio is performed under the condition where a high etching selective ratio with respect to the silicon nitride film is permitted, residues such as fluorocarbon are left in the opening portion during the progress of the etching operation. Thus, etching is interrupted.
As a technology for forming a multilayered metallization, double-trench metallization (called a “dual-damascene structure” in this industrial field) is employed frequently. When fabrication of the interlayer insulating film having the dual-damascene structure is performed, miniaturized dry etching process technology is required which is a combination of trench formation for burying two layered metallizations and contact hole formation for connecting the two layered metallizations to each other.
Hitherto, it is very difficult to control the depth of the trenches in the surface of the wafer when the trenches are formed in the interlayer insulating film. To realize the control, a method has been employed with which a silicon nitride film is inserted into the interlayer insulating film constituted by the silicon oxide film, so that the silicon nitride film is used as the stopper for the dry etching. When the dual-damascene structure having a complicated shape is formed, the stopper constituted by the silicon nitride film is required to control the depth of the trench metallization of the upper layer after the contact hole has been formed.
In the foregoing case, the silicon nitride film, which has a dielectric constant higher than that of the silicon oxide film, is contained adjacent to the metallization. Therefore, the wiring capacitance is enlarged excessively, causing the operation speed of the semiconductor device to be reduced. When the trenches are formed, partial etching of the interlayer insulating film constituted by the silicon oxide film occurs. Thus, ions are concentrated in the bottom corners of each trench, causing a shape called “trenching” to be formed in the corners of each trench. Therefore, the wiring metal cannot be easily buried in the trench.
Hitherto, an LSI of a type having a mixed structure so that a DRAM (Dynamic Random Access Memory) and a logic are mounted on one chip is structured such that the alignment margin (a fringe) in the logic portion is about ¼ of the alignment margin in the DRAM, owing to the difference in the design rule between the DRAM section and the logic section.
In an example case in which a contact hole is formed in an interlayer insulating film having the dual-damascene structure, the following step is employed: a dry etching condition where a high selectivity with respect to the etching stopper constituted by the silicon nitride film on the lower trench metallization is used to form the contact hole in the interlayer insulating film constituted by the silicon oxide film. Then, the silicon nitride film is removed, and then the wiring metal is buried in the contact hole and trenches of the upper metallization.
In the logic section, having a small alignment margin, a portion of the opening of the contact hole is sometimes deviated to the outside of the stopper constituted by the silicon nitride film which covers the lower trench metallization. Therefore, the interlayer insulating film constituted by the silicon oxide film which buries the side surface of the lower trench metallization easily encounters borderless etching that is cut during the step of forming the contact hole. Therefore, there arises a problem in that a fault in burying and a short-circuit fault of the wiring metal occur.
Hitherto, polysilane anti-reflective film is formed below the resist in the lithography step. When the resist is removed by performing O2 ashing after the pattern has been formed, a phenomenon undesirably occurs in that polysilane is oxidized. Thus, oxidized polysilane cannot easily be removed.
Also, with progress in the miniaturization and operating speed of semiconductor devices, the wiring structure has progressed from a single layer structure into a multi-layered structure so as to arrive at the stage that a semiconductor device having a multi-layered wiring structure including five or more layers has been developed and manufactured. However, with progress in the degree of miniaturization, the operating speed and the multi-layered structure, the signal transmission delay caused by the so-called “inter-wiring parasitic capacitance” and the wiring resistance is brought about as a serious problem.
Various measures are taken for avoiding the signal transmission delay. For example, Cu having a resistivity lower than that of Al is used as a wiring material in order to decrease the wiring resistance. Since it is very difficult to process a Cu film into the shape of the wiring by the dry etching process as in the prior art, a damascene structure is employed in the case of a Cu wiring. On the other hand, a so-called “low-k material” having a dielectric constant lower than that of SiO2 is used as an insulating material in order to decrease the inter-wiring parasitic capacitance.
However, with further progress in the degree of miniaturization of the semiconductor device in the future, it is expected that it will be difficult to cope with the signal transmission delay caused by the inter-wiring parasitic capacitance and the wiring resistance by simply employing the wiring structure using the low-k material and Cu in combination. Also, an additional problem is generated that the processing of the insulating film and the burying of the wiring material will be rendered difficult.